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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. i 1/26/07 copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services descri bed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. is63lv1024 is63lv1024l 128k x 8 high-speed cmos static ram 3.3v revolutionary pinout features ? high-speed access times: 8, 10, 12 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe options ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single 3.3v power supply ? packages available: ? 32-pin 300-mil soj ? 32-pin 400-mil soj ? 32-pin tsop (type ii) ? 32-pin stsop (type i) ? 36-pin bga (8mmx10mm) ? lead-free available description the issi is63lv1024/is63lv1024l is a very high-speed, low power, 131,072-word by 8-bit cmos static ram in revolutionary pinout. the is63lv1024/is63lv1024l is fab- ricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 w (typical) with cmos input levels. the is63lv1024/is63lv1024l operates from a single 3.3v power supply and all inputs are ttl-compatible. functional block diagram a0-a16 ce oe we 128k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 january 2007
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. i 1/26/07 is63lv1024 is63lv1024l pin configuration 32-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 pin descriptions a0-a16 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 data inputs/outputs v dd power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 pin configuration 32-pin tsop (type ii) (t) 32-pin stsop (type i) (h) pin configuration 36-mini bga (b) (8 mm x 10 mm) 1 2 3 4 5 6 a b c d e f g h a0 a1 nc a3 a6 a8 i/o4 a2 we a4 a7 i/o 0 i/o5 nc a5 i/o 1 gnd vdd vdd gnd i/o6 nc nc i/o 2 i/o7 oe ce a16 a15 i/o 3 a9 a10 a11 a12 a13 a14
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. i 1/26/07 is63lv1024 is63lv1024l absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd + 0.5 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc 1 , i cc 2 read h l l d out i cc 1 , i cc 2 write l l x d in i cc 1 , i cc 2 dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd com. ?1 1 a ind. ?5 5 i lo output leakage gnd v out v dd , outputs disabled com. ?1 1 a ind. ?5 5 notes: 1. v il = ?3.0v for pulse width less than 10 ns. operating range range ambient temperature v dd commercial 0c to +70c 3.3v 0.3v industrial ?40c to +85c 3.3v 0.15v
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. i 1/26/07 is63lv1024 is63lv1024l capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. is63lv1024l power supply characteristics (1) (over operating range) -8 ns -10 ns -12 ns symbol param eter test conditions min. max. min. max. min. max. unit i cc 1 v dd operating v dd = max., ce = v il com. ? 100 ? 95 ? 90 ma supply current i out = 0 ma, f = max. ind. ? 110 ? 105 ? 100 typ. (2) ?75 ?70 ?65 i sb ttl standby v dd = max., com. ? 35 ? 30 ? 25 ma current v in = v ih or v il ind. ? 40 ? 35 ? 30 (ttl inputs) ce v ih , f = max i sb 1 ttl standby v dd = max., com. ? 15 ? 15 ? 15 ma current v in = v ih or v il ind. ? 20 ? 20 ? 20 (ttl inputs) ce v ih , f = 0 i sb 2 cmos standby v dd = max., com. ? 1 ? 1 ? 1 ma current ce v dd ? 0.2v, ind. ? 1.5 ? 1.5 ? 1.5 typ. (2) ? 0.05 ? 0.05 ? 0.05 (cmos inputs) v in v dd ? 0.2v, or v in 0.2v, f = 0 notes: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.3v, t a = 25 o c. not 100% tested. is63lv1024 power supply characteristics (1) (over operating range) -8 ns -10 ns -12 ns symbol param eter test conditions min. max. min. max. min. max. unit i cc 1 v dd operating v dd = max., ce = v il com. ? 160 ? 150 ? 130 ma supply current i out = 0 ma, f = max. ind. ? 170 ? 160 ? 140 typ. (2) ? 105 ? 95 ? 75 ind. (@15 ns) ? 90 i sb ttl standby v dd = max., com. ? 55 ? 45 ? 40 ma current v in = v ih or v il ind. ? 55 ? 45 ? 40 (ttl inputs) ce v ih , f = max i sb 1 ttl standby v dd = max., com. ? 25 ? 25 ? 25 ma current v in = v ih or v il ind. ? 30 ? 30 ? 30 (ttl inputs) ce v ih , f = 0 i sb 2 cmos standby v dd = max., com. ? 5 ? 5 ? 5 ma current ce v dd ? 0.2v, ind. ? 10 ? 10 ? 10 typ. (2) ? 0.5 ? 0.5 ? 0.5 (cmos inputs) v in v dd ? 0.2v, or v in 0.2v, f = 0 notes: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.3v, t a = 25 o c. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. i 1/26/07 is63lv1024 is63lv1024l ac test loads ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1 and 2 read cycle switching characteristics (1) (over operating range) -8 ns -10 ns -12 ns symbol parameter min. max. min. max. min. max. unit t rc read cycle time 8 ? 10 ? 12 ? ns t aa address access time ? 8 ? 10 ? 12 ns t oha output hold time 2 ? 2 ? 2 ? ns t ace ce access time ? 8 ? 10 ? 12 ns t doe oe access time ? 4 ? 5 ? 6 ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? ns t hzoe (2) oe to high-z output 0 4 0 5 0 6 ns t lzce (2) ce to low-z output 3 ? 3 ? 3 ? ns t hzce (2) ce to high-z output 0 4 0 5 0 6 ns t pu ce to power up time 0 ? 0 ? 0 ? ns t pd ce to power down time ? 8 ? 10 ? 12 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v loading specified in figure 1. 2. tested with the loading specified in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. figure 1 output v t = 1.5v z out = 50 50 317 5 pf including jig and scope 351 output 3.3v figure 2
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. i 1/26/07 is63lv1024 is63lv1024l data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. i 1/26/07 is63lv1024 is63lv1024l write cycle switching characteristics (1,3) (over operating range) -8 ns -10 ns -12 ns symbol parameter min. max. min. max. min. max. unit t wc write cycle time 8 ? 10 ? 12 ? ns t sce ce to write end 7 ? 7 ? 8 ? ns t aw address setup time to 8 ? 8 ? 8 ? ns write end t ha address hold from 0 ? 0 ? 0 ? ns write end t sa address setup time 0 ? 0 ? 0 ? ns t pwe 1 (1) we pulse width ( oe high) 7 ? 7 ? 8 ? ns t pwe 2 (2) we pulse width ( oe low) 8 ? 10 ? 12 ? ns t sd data setup to write end 5 ? 5 ? 6 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 4 ? 5 ? 6 ns t lzwe (2) we high to low-z output 3 ? 3 ? 3 ? ns notes: 1. test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling ed ge of the signal that terminates the write. ac waveforms write cycle no. 1 (1,2 ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. i 1/26/07 is63lv1024 is63lv1024l ac waveforms write cycle no. 2 (1) ( we controlled, oe = high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. i 1/26/07 is63lv1024 is63lv1024l data retention waveform ( ce controlled) data retention switching characteristics symbol p arameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 ? 3.6 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v is63lv1024 ? 0.5 10 ma is63lv1024l ? 0.05 1.5 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ??ns note 1 : typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. i 1/26/07 is63lv1024 is63lv1024l is63lv1024 ordering information commercial range: 0c to +70c speed (ns) order part no. package 8 is63lv1024-8k 400-mil plastic soj IS63LV1024-8KL 400-mil plastic soj, lead-free 10 is63lv1024-10t tsop (type ii) is63lv1024-10j 300-mil plastic soj is63lv1024-10k 400-mil plastic soj 12 is63lv1024-12t tsop (type ii) is63lv1024-12j 300-mil plastic soj is63lv1024-12kl 400-mil plastic soj, lead-free industrial range: ?40c to +85c speed (ns) order part no. package 8 is63lv1024-8ki 400-mil plastic soj 10 is63lv1024-10ki 400-mil plastic soj 12 is63lv1024-12ti tsop (type ii)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. i 1/26/07 is63lv1024 is63lv1024l is63lv1024l ordering information commercial range: 0c to +70c speed (ns) order part no. package 8 is63lv1024l-8t tsop (type ii) is63lv1024l-8b mbga (8mmx10mm) 10 is63lv1024l-10t tsop (type ii) is63lv1024l-10tl tsop (type ii), lead-free is63lv1024l-10hl stsop (type i) (8mm x13.4mm), lead-free 12 is63lv1024l-12t tsop (type ii) is63lv1024l-12h stsop (type i) (8mm x13.4mm) is63lv1024l-12j 300-mil plastic soj is63lv1024l-12jl 300-mil plastic soj, lead-free is63lv1024l-12b mbga (8mmx10mm) industrial range: ?40c to +85c speed (ns) order part no. package 8 is63lv1024l-8ti tsop (type ii) is63lv1024l-8ji 300-mil plastic soj is63lv1024l-8ki 400-mil plastic soj is63lv1024l-8bi mbga (8mmx10mm) 10 is63lv1024l-10hi stsop (type i) (8mm x13.4mm) is63lv1024l-10jli 300-mil plastic soj, lead-free is63lv1024l-10kli 400-mil plastic soj, lead-free is63lv1024l-10tli tsop (type ii), lead-free 12 is63lv1024l-12bi mbga (8mmx10mm) is63lv1024l-12bli mbga (8mmx10mm), lead-free is63lv1024l-12ti tsop (type ii)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 10/29/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information 400-mil plastic soj package code: k notes: 1. controlling dimension: millimeters. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. reference document: jedec ms-027. seating plane 1 n e1 d e2 e b e a1 a c a2 b n/2+1 n/2 millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max no. leads (n) 28 32 36 a 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 a1 0.64 ? 0.025 ? 0.64 ? 0.025 ? 0.64 ? 0.025 ? a2 2.08 ? 0.082 ? 2.08 ? 0.082 ? 2.08 ? 0.082 ? b 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 c 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 d 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930 e 11.05 11.30 0.435 0.445 1 1.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 e1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e2 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc e 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc
copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 10/29/03 packaging information millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max no. leads (n) 40 42 44 a 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 a1 0.64 ? 0.025 ? 0.64 ? 0.025 ? 0.64 ? 0.025 ? a2 2.08 ? 0.082 ? 2.08 ? 0.082 ? 2.08 ? 0.082 ? b 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 c 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 d 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130 e 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 e1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e2 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc e 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information 300-mil plastic soj package code: j notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches sym. min. typ. max. min. typ. max. n0. leads 24/26 a ? ? 3.56 ? ? 0.140 a1 0.64 ? ? 0.025 ? ? a2 2.41 ? 2.67 0.095 ? 0.105 b 0.41 ? 0.51 0.016 ? 0.020 b 0.66 ? 0.81 0.026 ? 0.032 c 0.20 ? 0.25 0.008 ? 0.010 d 17.02 ? 17.27 0.670 ? 0.680 e 8.26 ? 8.76 0.325 ? 0.345 e1 7.49 ? 7.75 0.295 ? 0.305 e2 6.27 ? 7.29 0.247 ? 0.287 e 1.27 bsc 0.050 bsc seating plane 1 n e1 d e2 e b e a1 a b c a2
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 packaging information millimeters inches sym. min. typ. max. min. typ. max. n0. leads 28 a ? ? 3.56 ? ? 0.140 a1 0.64 ? ? 0.025 ? ? a2 2.41 ? 2.67 0.095 ? 0.105 b 0.41 ? 0.51 0.016 ? 0.020 b 0.66 ? 0.81 0.026 ? 0.032 c 0.20 ? 0.25 0.008 ? 0.010 d 18.29 ? 18.54 0.720 ? 0.730 e 8.26 ? 8.76 0.325 ? 0.345 e1 7.49 ? 7.75 0.295 ? 0.305 e2 6.27 ? 7.29 0.247 ? 0.287 e 1.27 bsc 0.050 bsc millimeters inches sym. min. typ. max. min. typ. max. n0. leads 32 a ? ? 3.56 ? ? 0.140 a1 0.64 ? ? 0.025 ? ? a2 2.41 ? 2.67 0.095 ? 0.105 b 0.41 ? 0.51 0.016 ? 0.020 b 0.66 ? 0.81 0.026 ? 0.032 c 0.20 ? 0.25 0.008 ? 0.010 d 20.83 ? 21.08 0.820 ? 0.830 e 8.26 ? 8.76 0.325 ? 0.345 e1 7.49 ? 7.75 0.295 ? 0.305 e2 6.27 ? 7.29 0.247 ? 0.287 e 1.27 bsc 0.050 bsc 300-mil plastic soj package code: j
integrated silicon solution, inc. packaging information plastic stsop - 32 pins package code: h (type i) notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e do not include mold flash protru- sions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic stsop (h - type i) millimeters inches symbol min max min max ref. std. n 32 a ? 1.25 ? 0.049 a1 0.05 ? 0.002 ? a2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 c 0.14 0.16 0.0055 0.0063 d 13.20 13.60 0.520 0.535 d1 11.70 11.90 0.461 0.469 e 7.90 8.10 0.311 0.319 e 0.50 bsc 0.020 bsc l 0.30 0.70 0.012 0.028 s 0.28 typ. 0.011 typ. 0 5 0 5 pk13197h32 rev. b 04/21/03 d1 seating plane c d 1 n e s b a1 a a2 e l
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. e 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information mini ball grid array package code: b (36-pin) notes: 1. controlling dimensions are in millimeters. mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 36 36 a ? ? 1.20 ? ? 0.047 a1 0.24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 7.90 8.00 8.10 0.311 0.315 0.319 d1 5.25bsc 0.207bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 8mm x 10mm millimeter inches sym. min. typ. max. min. typ. max. n0. leads 36 36 a ? ? 1.20 ? ? 0.047 a1 0.24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 9.90 10.00 10.10 0.390 0.394 0.398 d1 5.25bsc .207bsc e 7.90 8.00 8.10 0.311 0.315 0.319 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (36x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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